Parallel decimal accumulator



M y 1959 E. J. PETHERICK ET AL 2,886,242

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GEOFFREY G. ROWE-1H Invenfor- By M M W4 k P Attorneys United States Patent PARALLEL DECllVIAL ACCUMULATOR Edward John Petherick, Rowledge, near Famham, and Geofirey Charles Rowley, Sutton, England, assignors, by mesne assignments, to International Business Machines Corporation, New York, N.Y., a corporation of New York Application March 11, 1954, Serial No. 415,492

Claims priority, application Great Britain March 17, 1953 12 Claims. (Cl. 235-173) The present invention relates to digital computing engines working in the decimal scale of notation.

According to the present invention, a decimal digital computing engine comprises a parallel accumulator having a plurality of accumulator stages connected in a closed ring, means for propagating carry digits from one accumulator stage to the next in a predetermined sense of direction round the ring and defining means for defining any one of the accumulator stages as that assigned to store the most significant decimal digit.

According to a feature of the present invention, each accumulator stage comprises a counting device and a carry memory device arranged to store at least one carry digit during the time in which a number is being added to the accumulator.

Means may be provided for adding up to nine to each counting device during any one addition to the accumulator and the carry memory device may be arranged to store any single carry digit and to propagate the carry digit to the next counting device before any further addition to the accumulator.

An embodiment of the present invention will now be described, by way of example, with reference to specific electrical computing engine. Reference will now be made to the accompanying drawings, in which:

Figures 1 (a), (b) and (c) are diagrams explanatoryof the notation used in other figures for one of the circuit elements in logical circuits,

Figures 2 (a) and (b) are diagrams explanatory of the notation used in other figures for another of the circuit elements in the logical circuits.

Figure 3 is a logical circuit diagram of a recoder for recoding a four-element code representing a decimal digit into a five-element code representing the same digit,

Figure 4 is a circuit diagram of part of the arithmetical register of the computing engine,

Figure 5 is a circuit diagram of part of a control ring in the computing engine,

Figure 6 is a block-schematic diagram of part of the computing engine,

Figure 7 is a logical circuit diagram of a recoder-for recoding decimal digits stored in the accumulator of the computing engine into a four-element code,

Figure 8 is a graphical representation of voltage against time and is explanatory of the circuit shown in Figure 7,

Figure 9 is a logical circuit diagram of a ring accumulator,

Figure 10 is a logical circuit diagram of one stage of the accumulator shown in Figure 9 and also includes a 2,886,242 Patented May 12, 1959 "ice logical representation of part of one stage of the arithmetical register,

Figure 11 is a circuit diagram of part of the accumulator stage shown in Figure 10,

Figure 12 is a series of diagrams illustrating the timing of pulses applied to the arithmetical register, and other parts of the engine, during multiplication,

Figure 13 is a logical circuit diagram of a multiplier register, a sign register and their associated circuits,

Figure 14 is a logical circuit diagram of part of the pulsing unit indicated in Figure 6, v

Figure 15 is a logical diagram of a circuit for controlling the pulsing unit shown in Figure 14,

Figure 16 is a logical circuit diagram of an exponent register and its associated scale-of-ten counters,

Figures 17 (a) and (b) are logical circuit diagrams illustrating two alternative forms of arithmetical register, and

Figure 18 is a block-schematic diagram illustrating the general arrangement of the computing engine.

Some of the circuit elements illustrated in the accompanying drawings are described in the specification of United States Patent No. 2,686,632, issued August 17, 1954. As far as possible the notation defined in that specification will be used for the logical circuit diagrams in the present specification.

However, two of the circuit elements illustrated in the accompanying drawings have no counterpart described in the above-mentioned patent specification and will now be described with reference to Figures 1 and 2.

Figures 1 (b) and (0) show the notation which will-be used hereinafter to illustrate a circuit which will be termed hereinafter in the specification and appended claims as a trigger tube. The circuit employs a cold-cathode trigger tube in which a low current discharge between a subsidiary anode and cathode can be switched to a main anode-cathode path' by a pulse applied to a transfer electrode. We use the tube sold under the trade designation Gl/370K or G1/371K. The properties of this tube and its application are disclosed in a paper Some Recently Developed Cold Cathode Tubes and Associated Circuits which was published in the April, May and June 1952 issues of Electronic Engineering, at pages 152, 230 and 272, respectively. One useful property of these tubes is that once the discharge has been transferred to the main cathode-anode path a tube may be used to pass applied pulses. The tube may therefore act as a combined trigger and gate.

Figures 1 (b) and ('0) illustrate the schematic notation used by comparison with a simple equivalent circuit using more conventional symbols as shown in Figure 1(a) Figure 1(a) shows a trigger tube 301 having an anode load 302 and a cathode load 303. A positive pulse applied to the trigger electrode of the trigger tube via input 1 will flash the trigger tube provided its anode-to-cathode voltage is sufficiently great. The flashing of the trigger tube causes a change in the direct voltage at output 1. When the trigger tube is flashed, a negative pulse applied to input 2 will appear as a negative pulse at output 2. A long negative pulse (of about 25 microseconds duration) applied to the input designated put off 1 will put the trigger tube off (that is to say, cause the main cathodeanode discharge to cease) and also cause a negative pulse output at output 3. Those inputs and outputs are those generally used. However, other similar connections may or counting pulses down by a scale of ten.

be used. For example, a long positive pulse applied to the cathode of the trigger tube will put it off and a positive pulse may also be passed from the anode circuit to the cathode circuit.

Figures 1 (b) and show the schematic equivalents of Figure 1(a). The line drawn through the crosshatched portion of the oval 304, from say, input 2 to output 2 illustrates the main cathode-anode path through which pulses may be passed. In Figure l(b), the input -1-illustrates. the connection to the trigger electrode to put the trigger tube on. Output 1 illustrates a direct voltage output from the trigger tube circuit and the put ofi connection illustrates a means of putting off the trigger tube. nection and to the main cathode-anode path, as shown in Figure 1(a) indicated that the pulse used to put the trigger tube oft also serves to provide an output pulse at output 3.

Thiscomputing engine also employs scale-of-ten counters and we prefer to use a cold-cathode counting tube.

These tubes are well-known in the art and are sold under the trade names Dekatron and Nomotron. These tubes are generally called dekatrons. In these tubes a dicharge is set up between a central anode and one of ten surrounding cathodes. This discharge can be stepped to successive cathodes by feeding pulses to certain transfer electrodes. Nine of the cathodes are usually connected internally and access is given to that group and to the remaining cathode. This remaining cathode forms the output electrode and gives an output while the discharge remains on it. The tube thus counts stepping We prefer to use the tube sold under the trade designation GC.10D.

Figures 2 (a) and (b) illustrate the convention used to represent dekatrons in the logical circuit diagrams in this specification. Figure 2(a) shows a dekatron 305 and an input for counting on stepping pulses connecting to the stepping electrode of the dekatron. A counting pulse applied to the input causes the discharge in the dekatron to be stepped from one cathode to the next. The nine cathodes which have a common connection are represented at 306. When the discharge reaches the output cathode 307 an output is obtained from the output cathode.

Figure 2(b) shows the convention actually used in the logical circuit diagrams in this specification. Figure 2(b) shows diagrammatically an envelope 308, a central anode and ten surrounding cathodes. The input connected to the envelope is equivalent to the input for counting pulses shown in Figure 2(a) and the output is shown connected to a cathode (the output cathode).

,In Figures 17(a) and 17(b) of the drawings, switching tubes are illustrated. In these cases, inputs or outputs may be applied to or taken from any of the cathodes and connections to all the cathodes are thus shown.

Similar-1y an input or an output may be applied to or taken from the anode and a connection to the anode is, therefore, shown. The discharges in these switching tubes may also he stepped in a manner similar to the a four-element code in the main storage of the machine but in the arithmetical register they are represented by a five-element code. I

In the store, numbers are presented in the serial mode, and the code elements to each digit are presented simultaneously, that is to say, on four channels simultaneously. When the four-element code is used, the chan- A line connected to the put 0 connels will be referred to as the channels 1, 2, 3 and 9, and when the five-element code is used, the channels will be referred to as 1/8, 2/7, 3/6, 4/5 and 4. The codes used are represented in the following table:

Table 1 Four-element code Five-element code for the for storage Arithmetieal Register Digit Channels used Channels used x x 8 x x x 9 x In this table an x indicates that a pulse, or a voltage, is present on the channel indicated.

The use of the five-element code set out in Table -1 renders it a simple matter to take either the direct digit of an operand or its complement on 9.

At this stage it will be convenient to explain how the four-element code used in the store of the engine is translated into the five-element code used in the arithmetical register, and for this purpose reference is made to Figure 3. The four-element codes appear on the channels marked 1, 2, 3 and 9 at the left-hand side of the drawing and are translated to a five-element code on the channels 1/8, 2/7, 3/ 6, 4/5 and 4 at the right-hand side of the drawing. The voltages on these last channels may be set up by trigger tubes 11, 12, 13, 14 and 15.

The tubes 11, 12 and 13 are set respectively by the channels 1, 2 and 3 through the gates 16, 17 and 18, provided these gates are not inhibited. These gates are, however, inhibited when a voltage occurs simultaneously on any two of the channels 1, 2 and 3. The gates are, of course, inhibited by the output from the end gate 19 when the condition stated exists. The tube 14 is flashed when there is a voltage on the lines 1 and 3 or 2 and 3, because the output from the gate 19 will gate the voltage on the line 3 through the gate 111 to the tube 14. Finally the tube 15 will be operated when there is a voltage present on the channels 2 and 3 or on the channel 9; gate 112, of course, passes the voltages on the lines 2 and 3 to operate the tube 15. It will thus be seen that the codes are translated in accordance with Table 1.

. The states of the trigger tubes 11 to 15 may be read by applying a voltage pulse to an input line 113 in a manner to be explained hereinafter. The voltage pulse passes through those (if any) of the trigger tubes 11 to 15 which are flashed so that a pulse appears on none, one or two of the output channels l/8, 2/7, 3/6, 4/5 and 4 so as to represent one of the decimal digits 0 to 9 in the fiveelement code. The voltage pulse is also applied to an end element 114 the output of which is connected to an inhibiting connection on each of the trigger tubes 11 to 15. Thus, at the end of each voltage pulse, those trigger tubes which have been flashed are put 011.

The gate 19 is arranged to give an output when it receives an input on any two of the input lines. This gate may conveniently comprise three resistances fed separately with the input voltages and all connected at their ends remote from the input ends to a common resistance.

This common resistance may be arranged between the 

